The critical dimensions (CD) of a semiconductor device are the dimensions of the smallest features that can be formed during a manufacturing process. Device scaling has resulted in an increased integration density, which has resulted in a requirement for manufacturing processes capable of decreasing the size of the CD. A logic device has the critical dimension (CD) of a transistor in inverse proportion to integration density.
When a floating gate pattern having a CD of 130 nm or less is formed, the CD of the gate pattern as well as the CD of a space between the neighboring gate lines is often reduced to 100 nm or less.
In this case, in order to secure a depth of focus (DOF) margin using a KrF light source of 248 nm, the thickness of a photoresist (PR) layer must be thin. This gives rise to a trade-off problem that the PR layer must maintain a minimum thickness required when an etching process is performed. Without a sufficient DOF margin, pattern defects such as pattern deformation, pattern collapse, etc. occur.
One solution to this problem is to change manufacturing processes by, for example, selecting a material for the PR layer capable of using an ArF light source of 193 nm instead of the KrF light source to form a polysilicon transistor. However, in this case, it is also difficult to form a space between the neighboring gate patterns up to the CD of 100 nm or less.
Hereinafter, a conventional method for manufacturing a semiconductor device having a fine pattern using a KrF light source will be described.
A conventional method for manufacturing a semiconductor device will be described below with reference to the attached figures.
FIGS. 1A through 1G are sectional views illustrating a conventional method for manufacturing a semiconductor device.
Referring to FIG. 1A, a gate insulating layer 11, a polysilicon layer 12, a first insulating layer 13, and a bottom anti-reflection coating (BARC) 14 are deposited on a substrate 10.
Then, a photoresist (PR) layer is applied to an entire top surface of the substrate 10 having the BARC 14, and is selectively exposed and developed to form a PR layer pattern 15.
Here, the BARC 14 prevents a standing wave phenomenon. The standing wave phenomenon occurs during the PR layer exposure process, where light incident onto the substrate 10 interferes with light reflected on the substrate 10. This interference, or standing wave phenomenon, causes the pattern profile to be deteriorated after exposure and development of the PR layer.
Referring to FIG. 1B, a BARC pattern 14a is formed by selectively removing the BARC 14 using the PR layer pattern 15 as a mask.
Referring to FIG. 1C, a first insulating layer pattern 13a is formed by etching the first insulating layer 13 using the PR layer pattern 15 as a mask.
Referring to FIG. 1D, after removing the PR layer pattern 15 and the BARC pattern 14a, a second insulating layer 16 is formed on an entire top surface of the polysilicon layer 12 including the first insulating layer pattern 13a. 
Referring to FIG. 1E, the second insulating layer 16 is etched back to form sidewall spacers 16a on sidewalls of the first insulating layer pattern 13a. This etch-back process refers to a process of etching a target material on a plane at the same thickness by means of an anisotropic etching process.
Specifically, the second insulating layer 16 is etched so as to be completely removed from flat upper portions of both the polysilicon layer 12 and the first insulating layer pattern 13a, and to only remain on the sidewalls of the first insulating layer pattern 13a. In addition, often the sidewalls of the first insulating layer pattern 13a are partially etched on upper sides thereof.
Referring to FIG. 1F, a polysilicon layer pattern 12a is formed by etching the polysilicon layer 12 using the first insulating layer pattern 13a and the sidewall spacers 16a located on the opposite sides of the first insulating layer pattern 13a as a mask.
Referring to FIG. 1G, the first insulating layer pattern 13a and the sidewall spacers 16a, which remain on the polysilicon layer pattern 12a, are then removed.
The polysilicon layer pattern 12a formed in this way becomes a pattern for gate lines or electrodes.
In this conventional method for manufacturing a semiconductor device, the process may be complicated because the deposition and etching processes are repeated several times. Further, the number of pieces of equipment used increases because of the number of processes performed.